1. Field of Invention
This invention relates to a wiring structure for use in a semiconductor integrated circuit in which wiring capacitance is effectively reduced and operational speed is improved and a method of forming the wiring structure. This invention also relates to a semiconductor integrated circuit in which the advantages of a low resistance wiring are fully utilized while production and development costs are minimized.
2. Description of Related Art
Historically, in a semiconductor integrated circuit, as the design parameters or minimum feature sizes have been reduced by improved fabrication technologies, both the number of elements which can be integrated in a semiconductor chip and the operational speed have been improved. The main reason for improved operational speed is that the switching speed of transistors has been improved as the dimensions i.e., the gate length in the case of a MOS transistor, have been reduced.
However, if the design rule, usually expressed by the minimum gate length of a transistor, becomes less than about 0.5 xcexcm, the size reduction of this feature does not always ensure improved operational speed. The main reason for this is that signal propagation time over long distance wiring between circuit blocks within an integrated circuit chip tends to increase as the feature size decreases.
In other words, the resistance per unit length increases as the feature size decreases because of the decrease in the cross-sectional area of the wiring. In addition, the capacitance per unit length also increases as the feature size decreases because the space between wires is reduced while the height of the wires is kept almost constant. Also, the dimensions of the chip tends to increase as the design rule decreases because the number of transistors integrated onto the chip increases more rapidly compared to the decrease in the size of the transistor. Therefore, the average wiring length between the circuit blocks tends to increase as the design rule decreases. Accordingly, as feature size decreases the resistance of the wire and the capacitance between the wires increases, and the signal propagation time over the wiring between circuit blocks, which is roughly determined by the product of the resistance and the capacitance, tends to increase. Therefore, in order to improve the operational speed of a semiconductor integrated circuit, in particular, in a semiconductor integrated circuit with a design size of 0.5 xcexcm or less, the resistance of the wire and the capacitance between the wires needs to be reduced.
Conventionally, wiring mainly formed of aluminum or aluminum alloys (hereafter xe2x80x9caluminum-based wiringxe2x80x9d) was used for metal wiring in semiconductor integrated circuits. Silicon oxide formed by chemical vapor deposition (CVD) is generally used as a dielectric layer for the insulation between wires in the same wiring layer and for the insulation between upper and lower wiring layers. Pure silicon oxide has a dielectric constant of 3.9, while silicon oxide formed by CVD generally has a dielectric constant of approximately 4.0-4.4. The dielectric layer for the insulation between wiring layers is referred to as the xe2x80x9cinterlayer dielectric layerxe2x80x9d, while the dielectric layer for the insulation between wires in the same wiring layer is referred to as the xe2x80x9cintra-layer dielectric layerxe2x80x9d, when it is necessary to distinguish between these two dielectric layers. However, these dielectric layers are usually formed integrally, and are usually collectively referred to as the xe2x80x9cinterlayer dielectric layerxe2x80x9d.
In order to reduce wiring capacitance, use of insulating materials having lower dielectric constants than that of silicon oxide has been considered. At the same time, in order to reduce the wiring resistance, use of wiring mainly formed of metals having resistivities lower than that of aluminum, such as silver, copper and gold has been considered. Among them, wiring mainly formed of copper or copper alloy (hereafter xe2x80x9ccopper-based wiringxe2x80x9d) has been widely investigated.
Aluminum-based wiring is usually formed by depositing a metal film on the entire surface of an insulating layer followed by selectively etching unnecessary portions of the metal film (hereafter xe2x80x9cetching methodxe2x80x9d). In contrast, formation of copper-based wiring by forming grooves in a dielectric layer, followed by forming a copper or copper alloy film within the grooves, (hereafter xe2x80x9cdamascene methodxe2x80x9d) has been examined. (M. T. Bohr, IEEE International Electrons Devices Meeting Digest of Technical Papers (1995) p. 241, J. Paraszczak et al., IEEE International Electrons Devices Meeting Digest of Technical Papers (1993) p. 261).
The materials described below have been examined because they have lower dielectric constants than silicon oxide.
1) Fluorinated Silicon Oxide
A technology has been developed in which a fluorinated silicon oxide film is formed by CVD using an atmosphere in which a fluorine compound gas is added to a conventional silicon oxide CVD atmosphere. The dielectric constant of the fluorinated silicon oxide film is about 3.0-3.7, and it can be decreased by increasing the amount of added fluorine. In practice, however, the dielectric constant can be lowered only to about 3.3, since the film becomes hygroscopic if the amount of added fluorine is increased too much (H. Miyajima et al., Proceedings of Symposium on Dry Process, (1994), p. 133, R. Katsumata et al., Proceedings of Symposium on Dry Process, (1995), p. 269).
2) Siloxane SOG
For lower dielectric constant materials, various siloxane SOG (spin-on-glass) materials have been examined. In this technology, a coating solution which includes siloxane oligomers is coated on a substrate and cured to form a SOG film. The siloxane oligomer includes Sixe2x80x94O and Sixe2x80x94R (Rxe2x95x90H, CH3, C6H5 etc.) bonds. The dielectric constant of the SOG film is about 2.8-3.3. For example, hydrogen silsesquioxane SOG (B. T. Ahlbum et al., Proceedings of the 1st International Dielectrics for ULSI Multi-level Interconnection Conference (1995) p. 36) and methyl-siloxane SOG (K. Numata et al., Materials Research Society Symposium Proceedings, Vol. 381 (1995) p. 255) have been widely examined.
3) Organic Material
Organic materials, such as: polyimides, including BPDA-PDA, fluorinated polyimide, polyimide siloxane, fluorinated resin/siloxane copolymer, benzocyclobutene, parylene-F, poly(fluorinated naphthalane), amorphous Teflon(trademark), fluorinated poly(arylethers), cyclo-perfluorocarbon polymer, and fluorinated amorphous carbon have been examined as low dielectric constant materials. Many of these materials are formed by a coating method, such as spin coating. However, some of these materials, e.g., fluorinated amorphous carbon, are formed by CVD. See, for example, C. H. Ting et al., Materials Research Society Proceedings, Val. 381 (1995) p. 3 C.-1, Lang et al., Materials Research Society Proceedings, Val. 381 (1995) p. 45, M. Mills et al., 1st International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 269, S.-P. Jeng et al., Materials Research Society Symposium proceedings, Val. 381 (1995) p. 197, B. C. Auman, 1st International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 297, N. H. Hendricks et al., 1st International Dielectrics for ULSI Multilevel Interconnection Conference (1995) p. 283, K. Endo et al., Japanese Journal of Applied Physics, Vol. 35 (1996) p. 1348.
4) Porous Material
It is possible to decrease the dielectric constant by decreasing the density of the dielectric film. As an extreme example, a dielectric constant of 1 can be obtained by providing a vacuum or an inert gas between wires. One method of decreasing the density is to form pores in the dielectric film. For example, an organic porous material (K. R. Carter et al., Materials Research Society Symposium Proceedings. Vol 1. 381 (1995) p. 79) or an inorganic porous material, such as a gel type silica (U.S. Pat. No. 5,488,015), have been investigated. The later material is often referred to as Xerogel(trademark) or nano-porous silica. A dielectric constant of about 2.0 or below is reported. Another method is to remove a dielectric material which has been filled between the wires, after the wires and the dielectric material are formed. For example, a method in which a carbon material formed between wires is removed by heating in oxygen is reported in M. B. Anand et al. Symposium on VLSI Technology Digest of Technical Papers (1996) p. 82.
Among the above-mentioned materials described in the categories 1)-4), the fluorine silicone oxide of category 1) has a lower limit dielectric constant of about 3.3. Therefore, there is a limit in the ability to reduce the wiring capacitance. Accordingly, in order to reduce the capacitance more effectively, further investigation of the materials categorized above as 2), 3) and 4) are being pursued. Hereafter, when a material is simply called a xe2x80x9clow dielectric constant material,xe2x80x9d it means abovedescribed materials except for the material of 1) category, and also means other materials developed in the future having a dielectric constant of around 3.0 or below.
Although the materials mentioned above which have low dielectric constants have been extensively investigated, these materials are difficult to utilize in semiconductor integrated circuits. First, these materials generally have a lower heat resistance than silicon oxide, and are susceptible to deformation or decomposition by heat processing during the manufacturing process. Second, films of these materials generally do not adhere onto the underlying metal film, or vise versa. Third, some of these materials contain relatively large amount of water. Even if the material does not initially contain a significant amount of water, the material may deform during heat processing and become hygroscopic, thus adsorbing water during the subsequent processing steps. This contained or adsorbed water may be desorbed during the subsequent heat processing, and the desorbed water may cause various problems such as degradation of adhesion and metal corrosion. Fourth, the above-mentioned materials generally have lower mechanical strengths compared to silicon oxide. Therefore, formation of hillocks on the surface of the underlying metal film cannot be prevented.
Fifth, it is generally difficult to form via holes through which the lower wiring layer and the upper wiring layer are connected to each other in films of these materials. In the case of the conventional silicon oxide film, via holes can be formed by aisotropical plasma etching in a fluorine-based gas atmosphere using a resist as a mask followed by removing the resist mask by ashing, i.e., oxidation by active oxygen or oxygen containing species created by plasma excitation or other methods. This method cannot generally be utilized for films formed of the materials described above because the etching characteristics of many of these materials is similar to that of the resist. Therefore, a mask made of silicon oxide, silicon nitride or another inorganic material film, instead of a resist mask, is often used to form via holes in the film of a low dielectric constant material. A mask made of an inorganic material film is often referred to as a hard mask.
Even when a hard mask is utilized, a resist mask is used to form apertures in the hard mask. During removal of the resist mask used to form apertures in the hard mask, portions of the film at the apertures are exposed to the ashing atmosphere. Many of the materials with low dielectric constants tend to be easily oxidized by active oxygen in the ashing atmosphere. The oxidation makes the material hygroscopic. Therefore, conditions for removal of the resist mask should be carefully chosen to suppress oxidation of the material. Some of the materials with low dielectric constants can be etched using the resist mask. Even in these cases, the conditions for removal of the resist mask should be carefully chosen to suppress oxidation of the surface of the material exposed at the side walls of the via holes.
And sixth, the materials described above generally have low thermal conductivity compared to silicon oxide. Due to the low thermal conductivity, the joule heat produced in the wiring cannot be effectively dissipated and the wiring may thermally breakdown under high pulsed current stress.
Furthermore, even if the materials described above having lower dielectric constants are used, the wiring capacitance is not always reduced effectively. That is, an effective dielectric constant, i.e., a dielectric constant calculated from an actual capacitance value and dimensions of the wiring, does not always result in a reduced dielectric constant for the material. For example, FIG. 1 shows wires 218a, 218b and 218c of a wiring layer 218 which are disposed on the surface of an underlying dielectric layer 212 which is formed with a silicon oxide film deposited on a semiconductor substrate 210. In this case, even though an interlayer dielectric layer 220 of a material having a lower dielectric constant is formed between and on the wires, the electric field between the wires is not confined within the interlayer dielectric layer 220. Rather, the electric field spreads into the underlying dielectric layer 212, which is disposed immediately under the wiring layer. Therefore, since the underlying dielectric layer 212 is formed with a conventional silicon oxide film, the effective dielectric constant between the wires is not reduced to the dielectric constant of the material used to form the interlayer dielectric layer 220. This phenomenon is described in U.S. Pat. No. 5,646,440.
In order to overcome at least some of the difficulties described above for materials having low dielectric constants, these materials are often used in combination with other insulating films, such as silicon oxide, silicon oxynitride, silicon nitride, or the like. For example, to improve adhesion with an underlying wiring layer and to suppress hillock formation on the surface of the underlying metal film, an underlying silicon oxide film is first formed by CVD on the underlying wiring layer and then a low dielectric constant film is formed (J. T. Wetzel et al., Materials Research Society Symposium proceedings Val. 381 (1995) P. 217,Y. Homma et al., Proceedings of the 12st International Conference on VLSI Multilevel Interconnection Conference (1995) p. 457). This underlying film is also referred to as a liner film. Also, to improve adhesion of an upper wiring layer formed on an interlayer dielectric layer and to prevent corrosion of the upper wiring layer by water contained in the low dielectric constant film, an overlying film is formed on the low dielectric constant film. This overlying film is also referred to as a cap film. The cap film may also used as the hard mask to form via holes in the interlayer dielectric layer.
However, the silicon oxide film deposited by CVD has a dielectric constant of about 4.0 to 4.4. The silicon oxynitride or silicon nitride film has an even higher dielectric constant. Therefore, used of the underlying and/or overlying film has an adverse effect on the ability to reduce wiring capacitance.
In addition, if the underlying film or the overlying film is deposited on a vertical surface by a conventional method such as plasma CVD, the surface of the deposited film tends to overhang. For example, as shown in FIG. 2, if an underlying film 216 is deposited by a plasma CVD on a substrate having a wiring layer 218 including wires 218a, 218b and 218c with vertical side surfaces, the surfaces of the deposited underlying film 216 overhang on the side surfaces of the wires. The overhang of the underlying film 216 makes the following processes difficult. For example, if a low dielectric constant film 228 is formed on the substrate with this underlying film, voids 229 are formed between the wires. The voids 229 cause cracks in the interlayer dielectric layer 220. Further, the capacitance between the wires varies due to variation of the shape of the voids.
To overcome the difficulty of forming via holes in a low dielectric constant film, a structure has been proposed in which a conventional CVD dielectric film is used for the insulation between adjacent wiring layers, and the low dielectric constant material is used only for the insulation between wires in the same wiring layer (S. P. Jeng et al., Materials Research Society Symposium Proceedings, Vol. 337 (1994) p. 25). However, in this case, the electric field between the wires spreads into the conventional CVD dielectric film having a relatively high dielectric constant formed on the wiring layer. Therefore, the capacitance between the wires is even higher than the example shown in FIG. 1.
Forming a thermoconductive insulating layer, for example, a silicon nitride layer or an aluminum nitride layer, directly contacting the wires of a wiring layer to facilitate heat dissipation has been described in U.S. Pat. No. 5,476,817. However, silicon nitride and aluminum nitride have even higher dielectric constant than silicon oxide. Therefore, in this case, since the electric field between the wiring significantly spreads into the thermoconductive insulating layer having a higher dielectric constant, the capacitance between the wiring becomes even higher.
The previously mentioned U.S. Pat. No. 5,646,440 proposes a structure to effectively reduce the capacitance between the wires by making the thickness of a low dielectric constant film between the wires greater than the height of the wires. However, the proposed structure also uses an underlying film of silicon oxide, silicon oxynitride or silicon nitride. Therefore, the problems described above related to the underlying film are not overcome.
With respect to the wiring, it has been suggested that aluminum-based wiring be completely replaced by copper-based wiring. However, various problems related to the copper-based wiring must be resolved in order to cost effectively produce semiconductor integrated circuits which utilize copper-based wiring. A practical and economically feasible way to implement copper-based wiring in various semiconductor integrated circuit products has not been proposed.
In view of the aforementioned problems in the conventional systems, an object of the invention is to provide a wiring structure which effectively reduces the capacitance between wiring as well as a method of forming the wiring structure.
Another object of the invention is to provide a practical way to implement low resistance wiring, such as copper-based wiring, in semiconductor integrated circuit products so that the advantages of the low resistance wiring are fully utilized while the difficulties related to low resistance wiring are effectively overcome.
According to one aspect of the invention, a wiring structure for use in a semiconductor integrated circuit is provided which includes a wiring layer with at least two adjacent wires formed on an underlying dielectric layer over a semiconductor substrate, whereby the adjacent wires are disposed from each other with a space s1; and a dielectric layer is formed on the wiring layer which includes a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed at least between opposing side surfaces of the adjacent wires such that the low dielectric constant film contacts the opposing side surfaces and wherein a bottom level of the low dielectric constant film between the adjacent wires is lower than a bottom level of the adjacent wires by at least about 20% of s1.
The invention also provides a method of forming a wiring structure for use in a semiconductor integrated circuit which includes forming a wiring layer, including at least two adjacent wires on an underlying dielectric layer, over a semiconductor substrate, the adjacent wires are disposed with a space of s1; and forming a dielectric layer on the wiring layer including forming a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed at least between opposing side surfaces of the adjacent wires such that the low dielectric constant film contacts the opposing side surfaces, and such that a bottom level of the low dielectric constant film between the adjacent wires is lower than a bottom level of the adjacent wires by at least about 20% of s1.
According to another aspect of the invention, a wiring structure is provided for use in a semiconductor integrated circuit which includes a wiring layer including at least two adjacent wires formed on an underlying dielectric layer formed over a semiconductor substrate; and a dielectric layer including an underlying film having a dielectric constant lower than that of silicon oxide formed at least on opposing side surfaces of the adjacent wires, and a low dielectric constant film having a dielectric constant lower than that of the underlying film formed at least between the opposing side surfaces of the adjacent wires.
The underlying film is preferably formed of fluorinated silicon oxide. The fluorinated silicon oxide may also contain substantially no Si(xe2x80x94F)2 bonds.
In addition, a bottom level of the low dielectric constant film between the adjacent wires is lower than a bottom level of the adjacent wires.
A method of forming a wiring structure for use in a semiconductor integrated circuit is provided which includes the steps of forming a wiring layer, including at least two adjacent wires on an underlying dielectric layer, over a semiconductor substrate; and forming a dielectric layer including forming an underlying film having a dielectric constant lower than that of silicon oxide at least on opposing side surfaces of the adjacent wires, and forming a low dielectric constant film having a dielectric constant lower than that of the underlying film at least between the opposing side surfaces of the adjacent wires.
Preferably, forming the underlying film is performed by depositing a fluorinated silicon oxide film by high density plasma CVD. The high density plasma CVD may be performed so that the fluorinated silicon oxide film contains substantially no Si(xe2x80x94F)2 bonds.
According to another aspect of the invention, a wiring structure is provided for use in a semiconductor integrated circuit which includes a wiring layer including at least two adjacent wires formed on an underlying dielectric layer formed over a semiconductor substrate; and a dielectric layer including an underlying film formed at least on opposing side surfaces of the adjacent wires and a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed at least between the opposing side surfaces of the adjacent wires, wherein the opposing side surfaces of the adjacent wires are substantially vertical to a main surface of the semiconductor substrate and surfaces of the underlying film on the opposing side surfaces are positively sloped.
Preferably, substantial portions of the surfaces of the underlying film on the opposing side surfaces are positively sloped.
In addition, the underlying film is preferably formed of fluorinated silicon oxide having a dielectric constant lower than that of silicon oxide. The dielectric constant of the low dielectric constant film is lower than that of the underlying film. The fluorinated silicon oxide may include substantially no Si(xe2x80x94F)2 bonds.
Preferably, the bottom level of the low dielectric constant film is lower than that of the adjacent wires.
The invention also provides a method of forming a wiring structure for use in a semiconductor integrated circuit which includes the steps of forming a wiring layer, including at least two adjacent wires on an underlying dielectric layer, over a semiconductor substrate; and forming a dielectric layer including forming an underlying film at least on opposing side surfaces of the adjacent wires, and forming a low dielectric constant film having a dielectric constant lower than that of silicon oxide at least between the opposing side surfaces of the adjacent wires, wherein the opposing side surfaces of the adjacent wires are substantially vertical to a main surface of the semiconductor substrate, and surfaces of the underlying film on the opposing side surfaces are positively sloped.
The forming of an underlying film is preferably performed so that substantial portions of the surfaces of the underlying film on the opposing side surfaces are positively sloped.
Also preferably, the forming an underlying film is performed by a high density plasma CVD with a substrate bias. In addition, the dielectric constant of the low dielectric constant film is preferably lower than that of the underlying film, and the forming a low dielectric constant film is performed by a second high density plasma CVD with a substrate bias.
According to another aspect of the invention, a wiring structure is provided for use in a semiconductor integrated circuit which includes a wiring layer which includes at least two adjacent wires formed on an underlying dielectric layer over a semiconductor substrate; and a dielectric layer including an underlying film formed at least on opposing side surfaces of the adjacent wires and a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed at least between the adjacent wires, wherein a thickness of the underlying film on upper portions of the opposing side surfaces of the adjacent wires is smaller than that on lower portions of the opposing side surfaces.
The underlying film is preferably formed of fluorinated silicon oxide having a dielectric constant lower than that of silicon oxide, and the dielectric constant of the low dielectric constant film is lower than that of the underlying film.
A method of forming a wiring structure for use in a semiconductor integrated circuit is provided which includes the steps of forming a wiring layer, including at least two adjacent wires on an underlying dielectric layer, formed over a semiconductor substrate; and forming a dielectric layer including forming an underlying film at least on opposing side surfaces of the adjacent wires, and forming a low dielectric constant film having a dielectric constant lower than that of silicon oxide at least between the adjacent wires, wherein a thickness of the underlying film on upper portions of the opposing side surfaces of the adjacent wires is smaller than that on lower portions of the opposing side surfaces.
The forming of an underlying film is preferably performed by a high density plasma CVD with a substrate bias.
Another aspect of the invention provides a wiring structure for use in a semiconductor integrated circuit which includes an intra-layer dielectric layer, including a low dielectric constant film having a dielectric constant lower than that of silicon oxide, formed over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; side wall films having a second dielectric constant lower than that of silicon oxide formed on side walls of the groove; and a wiring layer including a wire formed in the groove.
The dielectric constant of the low dielectric constant film is preferably lower than that of the side wall films.
Also preferably, the side walls films are formed of fluorinated silicon oxide. The fluorinated silicon oxide may include substantially no Si(xe2x80x94F)2 bonds.
A method of forming a wiring structure for use in a semiconductor integrated circuit is also provided which includes the steps of forming an intra-layer dielectric layer including a low dielectric constant film having a dielectric constant lower than that of silicon oxide over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films having a second dielectric constant lower than that of silicon oxide on side walls of the groove; and forming a wiring layer including a wire formed in the groove.
Preferably, the dielectric constant of the low dielectric constant film is lower than that of the side wall films.
Also preferably, the forming of side wall films includes depositing a fluorinated silicon oxide film by high density plasma CVD. The high density plasma CVD deposition step may be performed such that the fluorinated silicon oxide film contains substantially no Si(xe2x80x94F)2 bonds.
According to another aspect of the invention, a wiring structure is provided for use in a semiconductor integrated circuit which includes an intra-layer dielectric layer including a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; side wall films formed on side walls of the groove; and a wiring layer including a wire formed in the groove, wherein the side walls of the groove are substantially vertical with respect to a main surface of the semiconductor substrate, and surfaces of the side wall films are positively sloped.
Substantial portions of the surfaces of the side wall films are preferably positively sloped.
Also preferably, the dielectric constant of the side wall films is lower than that of silicon oxide.
In addition, the side walls films are preferably formed of fluorinated silicon oxide. The fluorinated silicon oxide may include substantially no Si(xe2x80x94F)2 bonds.
A method of forming a wiring structure for use in a semiconductor integrated circuit is also provided which includes the steps of forming an intra-layer dielectric layer comprising a low dielectric constant film having a dielectric constant lower than that of silicon oxide over a surface of a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films on side walls of the groove; and forming a wiring layer including a wire in the groove, wherein the side walls of the groove are substantially vertical with respect to a main surface of the semiconductor substrate, and surfaces of the side wall films are positively sloped.
Substantial portions of the surfaces of the side wall films are preferably positively sloped.
The step of forming side wall films also preferably includes performing high density plasma CVD with a substrate bias. The step of forming a wiring layer includes forming at least one of a barrier layer and a seed layer by ionized sputtering.
The dielectric constant of the side wall films is preferably lower than that of silicon oxide.
According to another aspect of the invention, a wiring structure is provided for use in a semiconductor integrated circuit which includes an intra-layer dielectric layer including a low dielectric constant film having a dielectric constant lower than that of silicon oxide formed over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; side wall films formed on side walls of the groove; and a wiring layer including a wire formed in the groove, wherein a thickness of the side wall films on upper portions of the side walls of the groove is smaller than that on lower portions of the side walls.
A dielectric constant of the side wall films is preferably lower than that of silicon oxide.
The side walls films are preferably formed of fluorinated silicon oxide.
A method of forming a wiring structure for use in a semiconductor integrated circuit is also provided which includes forming an intra-layer dielectric layer including a low dielectric constant film having a dielectric constant lower than that of silicon oxide over a semiconductor substrate, the intra-layer dielectric layer having a groove formed in the low dielectric constant film; forming side wall films on side walls of the groove; and forming a wiring layer including a wire in the groove, wherein a thickness of the side wall films on upper portions of the side walls of the groove is smaller than that on lower portions of the side walls.
The forming step includes the step of forming side wall films by high density plasma CVD with a substrate bias.
The dielectric constant of the side wall films is preferably lower than that of silicon oxide.
According to another aspect of the invention, a semiconductor integrated circuit is provided which includes at least one aluminum-based wiring layer disposed over a semiconductor substrate; at least one low resistance wiring layer disposed over the at least one aluminum-based wiring layer; and at least one circuit block including a plurality of transistors disposed on the semiconductor substrate connected with each other by wires in the at least one aluminum-based wiring layer, wherein wires of a selected type of wiring are formed on the at least one low resistance wiring layer.
The selected type of wiring includes a long distance signal wiring connecting the circuit block to an I/O cell or to a second circuit block.
Also, the selected type of wiring preferably includes a portion of power bus wiring commonly provided for supplying electric power to substantial portion of the integrated circuit.
In addition, the selected type of wiring may include a portion of power bus wiring provided for improving current conduction capability of a corresponding portion of the power bus wiring formed on the at least one aluminum-based wiring layer.
The at least one circuit block also preferably includes a plurality of circuit blocks, and the selected type of wiring includes a portion of clock wiring commonly provided for delivering a clock signal to the plurality of circuit blocks.
The circuit block may preferably include at least one macro cell selected from a macro cell library. Further, the macro cell library may be developed without using a low resistance wiring.
The circuit block may include at least one macro cell which has been designed and verified without using a low resistance wiring.
The low resistance wiring layer may preferably be a copper-based wiring layer.
The at least one low resistance wiring layer preferably includes at least one pair of low resistance wiring layers that are provided for forming wires in mutually orthogonal directions.
A method of forming a semiconductor integrated circuit is also provided which includes the steps of forming at least one circuit block including a plurality of transistors disposed on a semiconductor substrate connected with each other by wires on at least one aluminum-based wiring layer disposed over the semiconductor substrate; and forming wires of a selected type of wiring on at least one low resistance wiring layer disposed over the at least one aluminum-based wiring layer.
According to another aspect of the invention, a semiconductor integrated circuit is provided which includes at least one aluminum-based wiring disposed over a semiconductor substrate; at least one low resistance wiring layer disposed over the at least one aluminum-based wiring layer; and at least one macro cell which has been designed and verified without using a low resistance wiring.
The macro cell can preferably be placed into the system described above without a substantial re-design.
The connections within the macro cell are mainly made by wires on the at least one aluminum-based wiring layer, and connections outside of the macro cell are mainly made by wires on the at least one low resistance wiring layer.
The connections within the macro cell are preferably mainly made by wires on the at least one aluminum-based wiring layer, and wires of a selected type of wiring are formed on the at least one low resistance wiring layer.
A method of designing a semiconductor integrated circuit is provided which includes the steps of placing at least one macro cell which has been designed and verified without using a low resistance wiring; and making connections outside of the macro cell mainly by wires on at least one low resistance wiring layer.
The macro cell can preferably be placed without a substantial re-design.
The step of making connections preferably includes making wires of a selected type of wiring on the at least one low resistance wiring layer.
The step of making connections further includes making connections within the macro cell mainly by wires on at least one aluminum-based wiring layer.
According to another aspect of the invention, an application specific semiconductor integrated circuit of one of a first and a second grade, is provided which includes at least one macro cell selected from a macro cell library commonly provided for the first and the second grade; and at least one aluminum-based wiring layer, wherein the semiconductor integrated circuit further includes at least one low resistance wiring layer only when the grade is a preselected one.
The macro cell library is preferably developed without using a low resistance wiring.
The semiconductor integrated circuit also includes, if the grade is the preselected one, at least one second macro cell selected from a second macro cell library provide only for the preselected one of the grades.
The invention further provides a method of designing an application specific semiconductor integrated circuit of one of a first and a second grade, which includes the steps of selecting at least one macro cell from a macro cell library commonly provide for the first and the second grade; and placing the selected macro cell on the semiconductor integrated circuit, wherein the method further comprises making connections outside of the macro cell by using wires on at least one low resistance wiring layer only when the grade is a preselected one.